Mr. DHARMESHKUMAR PATEL

Faculty Details


  • Designation : Assistant Professor
  • Qualification : Ph D (pursuing)
  • Experience : 10 Years
  • Area Of Interest : VLSI, Channel coder, Embedded System

Educational Qualification

Ph D (pursuing)
M. Tech (VLSI & ES)
SVNIT, Surat
B. E (Electronics)
SCET, Surat
Diploma (EC)
TEB, Gandhinagar

Work Experiance

SFI college teaching experiance: 04 year

Government Engineering College: Since July 2009

Skills and knowledge

Embedded system design

VLSI system design
Channel coding


Courses Taught

Microprocessor ARM, 8086, 8085

Micro controller 8051, ATMEGA32
Embedded System
VLSI technology and design
Analog Circuit Design 
Analog Electronics
Digital Electronics
Analog & Digital Communication 

Training and Workshop

Induction Training Programme Phase-I

Induction Training Programme Phase-II
Introduction to Robotics
VLSI Design Fundamentals
VLSI PREFAB IMAGE TOOL
VLSI System Design
2017 Summer School on Cyber Physical System
BASICS OF SCADA & DCS PCS - 7

Portfolios

GTU Coordinator

Training & Placement cell member

Research Project

Channel coder design

Publication

Design and implementation of quasi cyclic low density parity check (QC-LDPC) code on FPGA

Electronic ISBN: 978-1-5090-4442-9
Publisher: IEEE


Academic Projects

Final year projects


Patent filed

nil

Professional Membership

Apply for ISTE lifetime membership

Expert Lectures

nil

Award

nil